1. Field of the Invention
The present invention relates to flash memory devices, and more specifically, to NAND-type flash memory devices having a uniform program speed.
2. Discussion of Related Art
A flash memory is a type of non-volatile memory that can maintain data when power is off and can be electrically programmed and erased. It does not need a refresh function of rewriting data on a predetermined cycle. In this case, the term “program” refers to an operation of writing data into memory cells, and the term “erase” refers to an operation of erasing data from a memory. This flash memory device can be largely classified into a NOR-type and a NAND type depending on the structure and operation condition of cells. In the NOR-type flash memory, the source of each memory cell transistor is connected to a ground terminal (VSS), and program and erase can be performed on a predetermined address. The NOR-type flash memory has been usually used for fields requiring a high-speed operation. On the other hand, in the NAND-type flash memory, a plurality of memory cell transistors is serially connected to form one string, and one string is connected to the source and drain. The NAND-type flash memory has been usual used for fields such as high-integration data retention.
FIG. 1 is a layout diagram showing the configuration of a unit cell string of a common NAND-type flash memory device.
Referring to FIG. 1, a unit cell string of the NAND-type flash memory device includes a source select transistor SST connected to a common source line (not shown), a drain select transistors DST connected to a bit line (not shown), and memory cells MC0 to MC31 serially connected between the source select transistor SST and the drain select transistors DST. Furthermore, the gate of the drain select transistors DST is connected to a drain select line DSL, the gate of the source select transistor SST is connected to a source select line SSL, and the gates of the memory cells MCC1 to MC31 are connected to word lines WL0 to WL31, respectively. In this case, the number of the memory cells MC serially connected between the source select transistor SST and the drain select transistors DST is 16, 32, or 64 in consideration of a device and density.
In the unit cell string structure as shown in FIG. 1, the program speed of the memory cells MC0 and MC31 connected to the first and last word lines WL0 and WL31 is slower than that of the remaining memory cells MC1 to MC30. This is because the first word line WL0 is adjacent to the source select line SSL and the last word line WL31 is adjacent to the drain select line DSL.
To be more specific, in a program operation, a program prohibit voltage (Vpass) is applied to non-selected word lines, whereas the ground voltage (VSS) is applied to the source select line SSL and the power supply voltage (VCC) is applied to the drain select line DSL. If so, the memory cells MC0 and MC31 experience interference by a voltage of the source select transistor SST and the drain select transistors DST, so that the program speed of the memory cells MC0 and MC31 becomes slower than that of the remaining memory cells MC1 to MC30.
FIG. 2 is a graph showing a threshold voltage depending on each word line in FIG. 1. A low threshold voltage corresponds to a slow program speed.
From FIG. 2, it can be seen that the threshold voltage (Vt) of the memory cell MC31 connected to the last word line WL31 that is the nearest to the drain select line DSL is the lowest, and the threshold voltage (Vt) of the memory cell MC0 connected to the first word line WL0 that is the nearest to the source select line SSL is the second lowest.
As described above, if the threshold voltage of particular memory cells (for example, MC0 and MC31 adjacent to DST and SST) is lower than that of the remaining memory cells MC1 to MC30, the program speed of the NAND-type flash memory device becomes non-uniform and distribution of the threshold voltage with a chip widens. This results in a degraded performance of the NAND-type flash memory devices.